Director of AMS Verification

We are seeking a visionary and technically accomplished Analog and Mixed-signal Verification Leader to found and lead our central AMS SoC Verification Team. In this role, you will architect and drive a worldclass verification strategy that elevates our mixedsignal rigor, and ensures firstpass success for increasingly complex mixed-signal SoC designs. You will architect an enterprise-wide verification platform that leverages best-in-class tools, modern methodologies, and scalable automation-while championing the adoption of reusable verification IP and standardized flows across the company. By introducing advanced AMS verification techniques, enforcing coverage-driven discipline, and operationalizing a robust reusable infrastructure, you will drastically reduce functional escapes and shorten product cycle times. This is a transformative leadership role, reporting to the Sr. Director of EDA Engineering, where you will not only build a high-impact organization from the ground up but also shape the verification foundation for our next generation of silicon innovation.

• Define and implement a modern AMS SoC verification methodology using industry-best practices, automation, and coverage-driven techniques
• Architect and grow an enterprise-wide verification platform leveraging best-in-class EDA tools, standardized flows, and scalable infrastructure
• Collaborate closely with design and verification leaders across the company to drive continuous improvement
• Bridge the gap between Design and Test with scalable methodologies to verify test program prior to tape-out and driving traceability all the way from requirements to ATE
• Drive adoption of reusable Verification IP (VIP) and establish common libraries, models, and testbench components to improve consistency and efficiency across teams
• Research, evaluate, and deploy AI/ML tools and techniques to enhance verification quality, predict bugs earlier, enable intelligent coverage closure, and improve overall efficiency
• Develop and enforce verification quality metrics, including functional coverage, mixed-signal assertions, and convergence criteria to prevent functional escapes.
• Develop a high-performing verification team, mentor engineers, and foster a culture of innovation, and technical excellence

• Bachelor's degree or higher in Computer Science, Computer Engineering, or related field
• 20+ years of experience in deluvering best in class mixed-signal verification solutions in complex SoCs in both individual contributor and leadership roles
• Expert-level knowledge of analog, digital, and mixed-signal SoC verification methodologies, including UVM, real number modeling, AMS simulation techniques, and metric driven verification.
• Strong understanding of complex SoC integration, mixed-signal interfaces, behavioral modeling, and end to end verification flows.
• Hands-on proficiency with industry-leading verification tools and platforms, including mixed-signal simulators, waveform analysis tools, regression systems, and enterprise-scale verification infrastructure.
• Proven ability to design and standardize enterprise verification environments, including reusable VIP, shared libraries and frameworks to continuously verify the model against design
• Deep familiarity with AI/ML technologies applied to verification, such as generation of verification harness from specs, end-to-end RCA, model generation and agentic flows that provide a true top-down verification system.
• Demonstrated experience building, scaling, and mentoring high-performing verification teams, including hiring senior technical talent and establishing a culture of rigor and technical excellence.
• Proficiency in automation and scripting-especially Python-to build scalable regression systems, tool integration, data pipelines, and workflow automation that improves team efficiency and quality
• Excellent cross-functional communication and leadership skills, enabling effective alignment with analog design, digital design, architecture, test engineering, and EDA/tool teams.

• Experience with formal verification, including property checking, assertion development, and formal methods to complement simulation-based verification
• Experience with emulation platforms (e.g., Palladium, Veloce, Zebu) to validate mixed-signal subsystems and accelerate system-level verification
• Background in functional safety standards (e.g., ISO 26262, IEC 61508), including safety analysis, FMEDA inputs, and verification practices targeting safety-critical SoCs.