ASIC Design Engineer

Ciena
paid holidays, sick time, 401(k)
United States, California, Petaluma
1465 North McDowell Boulevard (Show on map)
Jul 23, 2025
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We're a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact. As an ASIC Design Engineer at Ciena, you will be a pivotal force in the development of high-performance ASICs that are integral to our cutting-edge networking solutions. Under the direction of the Director of ASIC Engineering, your role involves a critical blend of innovation and precision. You will define, design, and implement complex digital blocks, ensuring the creation of innovative and reliable hardware that propels Ciena's market leadership. How You Will Contribute: Define comprehensive block-level design documents, including interface protocols, block diagrams, and transaction flows, ensuring alignment with system requirements. Perform RTL coding and engage in function/performance simulation, debugging, and various checks (Lint, CDC, FV, UPF) to maintain high design standards. Participate in synthesis, timing and power closure, and the bring-up of FPGA/silicon, collaborating closely with cross-functional teams to meet project timelines. Develop and execute detailed test plans and coverage analysis for block and SOC-level verification, enhancing the reliability and performance of our products. Develop test benches and tests for FPGAs and ASICs. The Must Haves: Bachelor of Science degree in Electrical Engineering coupled with proven experience ASIC development with Verilog. Experience with ASIC design verification, synthesis, timing/power analysis and DFT. Experience with modern SoC design architectures. ARM/MIPS type processor cores. Strong debug and lab experience. Assets: Master of Science or PhD in Electrical Engineering. Knowledge of high performance and low power design techniques. Experience with Ethernet, Networking, and Data Communications Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture Develop diagnostic software for FPGAs Pay Range: The annual salary range for this position in California is $130,900 - $209,100. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. Not ready to apply? Join our Talent Community to get relevant job alerts straight to your inbox. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is anEqual Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.