Component Engineering - Technical Lead

The Cisco Technology and Quality team provides outstanding customer value through technical innovation and best in class quality solutions. The candidate will be a Cisco resident technical expect for SERDES components and be the SME interface to Cisco Business Units, Engineering, Vendors and other Supply Chain organizations.

As a senior member of our component quality and reliability team, you will have the opportunity to participate in the selection, design, validation, qualification, and failure analysis of all SERDES/PCIe components. Your goal will be to create processes and tools that assist system design engineering, component quality and reliability teams, diagnostics/test development teams, and suppliers in developing best-in-industry practices around SERDES components. You will also help understand vendors' roadmaps, review RFQs, and select components and/or IP for next-generation products. Additionally, you will work with vendors to conduct end-to-end failure analysis on all SERDES-based issues impacting components and systems.

• Strong teamwork & collaboration skills.
• Excellent problem solving & effective conflict resolution skills.
• Ability to study and analyze internal and external resources to lead SERDES IP selections and discussions.
• Understanding of SERDES calibration, including the selection of equalization parameters.
• Knowledge of semiconductor components development: design, fabrication, characterization, qualification, testing, quality, reliability, failure analysis.
• Solid understanding of semiconductor device reliability testing and characterization such as HTOL, ELFR, LU, ESD, etc

• BS/MS in Electrical Engineering / Computer Engineering or related fields
• 8+ years' experience working with various high-speed SERDES architectures (NRZ, PAM4) and protocols.
• Hands on experience with SERDES blocks, such as CTLE, DFE, FFE, CDR, ADC, DAC, VGA/PGA, filters, and PLLs, including their characterization and debugging
• Experience with test and measurement equipment such as high-speed oscilloscopes and BERTs to measure and understand BER, FEC, etc.
• Hands on experience with SERDES signal integrity, eye diagrams, Bathtub Curves, etc.

• Experience with Ethernet, PCIe, and other high-speed protocol layers in a 10G+ environment is a definite plus.

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